1. Field of the Invention
The present invention relates to a method for programming a plurality of memory cells of a nonvolatile semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices are devices in which data can be stored and from which stored data can be retrieved. Semiconductor memory devices can be classified into volatile memory and nonvolatile memory. The volatile memory needs a power supply to retain data while the nonvolatile memory can retain data even when power is removed. Therefore, the nonvolatile memory devices have been widely used in applications in which power can be interrupted suddenly.
The nonvolatile memory devices comprise electrically erasable and programmable ROM cells, known as flash EEPROM cells. FIG. 1 shows a vertical cross-section of a flash EEPROM cell 10. Referring to FIG. 1, an N-type source region 13 and an N-type drain region 14 are formed on a P-type substrate or a bulk region 12. A p-type channel region is formed between the source region 13 and the drain region 14. A floating gate 16, which is insulated by an insulating layer 15, is formed on the P-type channel region. A control gate 18, which is insulated by another insulating layer 17, is formed on the floating gate 16.
FIG. 2 shows threshold voltages of the flash EEPROM cell 10 during program and erase operations. Referring to FIG. 2, the flash EEPROM cell 10 has a higher threshold voltage range (about 6 to 7V) during the program operation, and has a lower threshold voltage range (about 1 to 3V) during the erase operation.
Referring to FIGS. 1 and 2, during the program operation, hot electrons need to be injected from the channel region adjacent to the drain region 14 to the floating gate electrode, so that the threshold voltage of the EEPROM cell increases. In contrast, during the erase operation, the hot electrons injected into the floating gate 16 during the program operation need to be removed, so that the threshold voltage of the EEPROM cell decreases. Therefore, the threshold voltages of the EEPROM cell are varied after the program and erase operation.
One prior art method for programming an EEPROM cell is to apply a high voltage to the drain of the EEPROM cell transistor. For example, if the number of EEPROM cell transistors to be programmed is eight, a high voltage will be applied to the drain of each EEPROM cell transistor at one time in sequence. Therefore, the high voltage will be applied to the entire EEPROM cell transistors eight times. After the program operation has been performed on all eight EEPROM cell transistors, a verify operation is performed to check whether all the EEPROM cells are completely programmed. If all the memory cells are completely programmed, the programming of the memory cells is finished and further program operation is not performed. In contrast, if any one of the memory cells fails to be programmed, a second programming of the memory cells is performed. In the second programming, the high voltage is applied to the drain of each EEPROM cell transistor at one time in sequence. After the high voltage is applied to the entire EEPROM cell transistors eight times, the verify operation is repeated. The program and verify operations will be repeated until all the threshold voltages of the EEPROM cell transistors to be programmed reach a preset value (for example, 6V).
As described above, in the conventional program operation, the time required for the entire program operation increases in proportion to the number of programming steps to be repeated. In addition, a verify operation is required after each program operation for checking whether the current threshold voltages of the memory cell transistors to be programmed have reached a preset value. Therefore, the duration of the entire program is further increased by inserting multiple verify operation steps. Also, the memory device requires more complex circuits to perform the verify operation. In order to solve the foregoing problems, there is a need to provide an improved programming method.